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    ET1100-EtherCAT從站協議芯片 - EtherCAT從站 - 關鍵詞:Ethercat 芯片

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    ET1100-EtherCAT從站協議芯片

    關鍵詞: ET1100,EtherCAT從站

    簡介:EtherCAT Slave Controller OverviewAn EtherCAT Slave Controller (ESC) takes care of the EtherCAT communication as an interfacebetween the EtherCAT fieldbus and the slave application. This document covers the followingBeckhoff ESCs: ASIC implementations (ET1100, ET1200), functionally fixed binary configurations forFPGAs (ESC20), and configurable IP Cores for FPGAs (ET1810/ET1815).Table 1: ESC Main F...
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    產品說明:

    EtherCAT Slave Controller Overview

    An EtherCAT Slave Controller (ESC) takes care of the EtherCAT communication as an interface

    between the EtherCAT fieldbus and the slave application. This document covers the following

    Beckhoff ESCs: ASIC implementations (ET1100, ET1200), functionally fixed binary configurations for

    FPGAs (ESC20), and configurable IP Cores for FPGAs (ET1810/ET1815).

    Table 1: ESC Main Features

    Feature

    ET1200

    ET1100

    IP Core

    ESC20

    Ports

    2-3 (each
    EBUS/MII,
    max. 1xMII)

    2-4 (each
    EBUS/MII)

    2-3 MII or
    2 RMII

    2 MII

    FMMUs

    3

    8

    0-8

    4

    SyncManagers

    4

    8

    0-8

    4

    RAM [KByte]

    1

    8

    1-60

    4

    Distributed Clocks

    64bit

    64bit

    32/64bit

    32bit

    Process Data Interfaces

    Digital I/O

    16bit

    32bit

    8-32bit

    32bit

    SPI Slave

    Yes

    Yes

    Yes

    Yes

    8/16 bit μController

    -

    Async/Sync

    Async

    Async

    On-chip bus

    -

    -

    Avalon/OPB

    -

     

    The general functionality of an ESC is shown in Figure 1:

     

    Figure 1: EtherCAT Slave Controller Block Diagram

    EtherCAT Slave Controller Function Blocks

    EtherCAT Interfaces (Ethernet/EBUS)

    The EtherCAT interfaces or ports connect the ESC to other EtherCAT slaves and the master. The

    MAC layer is integral part of the ESC. The physical layer may be Ethernet or EBUS. The physical

    layer for EBUS is fully integrated into the ASICs. For Ethernet ports, external Ethernet PHYs connect

    to the MII/RMII ports of the ESC. Transmission speed for EtherCAT is fixed to 100 Mbit/s with Full

    Duplex communication. Link state and communication status are reported to the Monitoring device.

    EtherCAT slaves support 2-4 ports, the logical ports are numbered 0-1-2-3, diverly they were

    denoted by A-B-C-D.

    EtherCAT Processing Unit

    The EtherCAT Processing Unit (EPU) receives, analyses and processes the EtherCAT data stream. It

    is logically located between port 0 and port 3. The main purpose of the EtherCAT Processing unit is to

    enable and coordinate access to the internal registers and the memory space of the ESC, which can

    be addressed both from the EtherCAT master and from the local application via the PDI. Data

    exchange between master and slave application is comparable to a dual-ported memory (process

    memory), enhanced by special functions e.g. for consistency checking (SyncManager) and data

    mapping (FMMU). The EtherCAT Processing Units contains the main function blocks of EtherCAT

    slaves besides Auto-Forwarding, Loop-back function, and PDI.

    Auto-Forwarder

    The Auto-Forwarder receives the Ethernet frames, perdivs frame checking and forwards it to the

    Loop-back function. Time stamps of received frames are generated by the Auto-Forwarder.

    Loop-back function

    The Loop-back function forwards Ethernet frames to the next logical port if there is either no link at a

    port, or if the port is not available, or if the loop is closed for that port. The Loop-back function of port 0

    forwards the frames to the EtherCAT Processing Unit. The loop settings can be controlled by the

    EtherCAT master.

    FMMU

    Fieldbus Memory Management Units are used for bitwise mapping of logical addresses to physical

    addresses of the ESC.

    SyncManager

    SyncManagers are responsible for consistent data exchange and mailbox communication between

    EtherCAT master and slaves. The communication direction can be configured for each SyncManager.

    Read or write transactions may generate events for the EtherCAT master and an attached μController

    respectively.

    Monitoring

    The Monitoring unit contains error counters and watchdogs. The watchdogs are used for observing

    communication and returning to a safe state in case of an error. Error counters are used for error

    detection and analysis.

    Reset

    The integrated reset controller observes the supply voltage and controls external and internal resets

    (ET1100 and ET1200 ASICs only).

    PHY Management

    The PHY Management unit communicates with Ethernet PHYs via the MII management interface. This

    is either used by the master or by the slave. The MII management interface is used by the ESC itself

    for restarting autonegotiation after receive errors with the enhanced link detection mechanism, and for

    the optional MI link detection and configuration feature.

    Distributed Clock

    Distributed Clocks (DC) allow for precisely synchronized generation of output signals and input

    sampling, as well as time stamp generation of events. The synchronization may span the entire

    EtherCAT network.

    Memory

    An EtherCAT slave can have an address space of up to 64Kbyte. The first block of 4 Kbyte (0x0000-

    0x0fff) is used for registers and user memory. The memory space from address 0x1000 onwards is

    used as the process memory (up to 60 Kbyte). The size of process memory depends on the device.

    The ESC address range is directly addressable by the EtherCAT master and an attached μController.

    Process Data Interface (PDI) or Application Interface

    There are several types of PDIs available, depending on the ESC:

    Digital I/O (8-32 bit, unidirectional/bidirectional, with DC support)

    SPI slave

    8/16 bit μController (asynchronous or synchronous)

    On-chip bus (e.g., Avalon for Altera FPGAs or OPB for Xilinx FPGAs)

    General purpose I/O

    The PDIs are described in Section III of the particular ESC, since the PDI functions are highly

    depending on the ESC type.

    ESI EEPROM

    One non-volatile memory is needed for ESC configuration and device description, typically an I²C

    EEPROM. If the ESC is implemented as an FPGA, a second non-volatile memory is necessary for the

    FPGA configuration code.

    Status / LEDs

    The Status block provides ESC and application status indivation. It controls external LEDs like the

    application RUN LED and port Link/Activity LEDs.

      ET1100datasheet.pdf (6.6MBytes)

    參數資料:
    ET1100-EtherCAT從站協議芯片ET1100,EtherCAT從站
    該文章系原廠商文章翻譯,不通之處請參考原文
    價格列表: ET1100-EtherCAT從站協議芯片ET1100,EtherCAT從站
    葩星訂貨號 訂貨號 產品名稱 報價 品牌  
    PXO_2477 ET1100-0002芯片 ET1100-0002芯片 198 ~ 253 ixxat
    PXO_2502 IT-E132 USB通訊線IT-E132 423 ~ 541 艾德克斯
    相關產品: ET1100-EtherCAT從站協議芯片ET1100,EtherCAT從站
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